ENABLING EFFICIENT AND SCALABLE DRAM READ DISTURBANCE MITIGATION VIA NEW EXPERIMENTAL INSIGHTS INTO MODERN DRAM CHIPS: Prof. Dr.

Abstract

Improvements in main memory storage density are primarily driven by technology node scaling, which causes DRAM cell size and cell-to-cell distance to reduce significantly. Unfortunately, technology scaling negatively impacts the reliability of DRAM chips by exacerbating DRAM read disturbance, i.e., accessing a row of DRAM cells can cause bitflips in data stored in other physically nearby DRAM rows. DRAM read disturbance 1) can be reliably exploited to break memory isolation, a fundamental principle of security and privacy in memory subsystems, and 2) existing defenses against DRAM read disturbance are either ineffective or prohibitively expensive. Therefore, it is critical to mitigate DRAM read disturbance efficiently to ensure robust (reliable, secure, and safe) execution in future DRAM-based systems. We define two research problems to address this challenge. First, protecting DRAM-based systems becomes increasingly more expensive over generations as technology node scaling exacerbates the vulnerability of DRAM chips to DRAM read disturbance. Second, many previously proposed DRAM read disturbance solutions are limited to systems that can obtain proprietary DRAM circuit design information about the physical layout of DRAM rows. This dissertation tackles these two problems in three sets of works. First, we build a detailed understanding of DRAM read disturbance by rigorously characterizing the read disturbance vulnerability of off-the-shelf modern DRAM chips under varying properties of 1) temperature, 2) memory access patterns, 3) spatial features of victim DRAM cells, and 4) voltage. Our novel observations demystify the large impact of these four properties on DRAM read disturbance and explain their implications on future DRAM read disturbance-based attacks and solutions. Second, we propose new memory controller-based mechanisms that mitigate read disturbance bitflips efficiently and scalably by leveraging insights into DRAM chip internals and memory controllers. Our mechanisms significantly reduce the performance overhead of maintenance operations that mitigate DRAM read disturbance by leveraging 1) subarray-level parallelism and 2) variation in read disturbance across DRAM rows in off-the-shelf DRAM chips. Third, we propose a novel solution that does not require proprietary knowledge of DRAM chip internals to mitigate DRAM read disturbance efficiently and scalably. Our solution selectively throttles unsafe memory accesses that might cause read disturbance bitflips. We demonstrate that it is possible to mitigate DRAM read disturbance efficiently and scalably with worsening DRAM read disturbance vulnerability over generations by 1) building a detailed understanding of DRAM read disturbance, 2) leveraging insights into DRAM chips and memory controllers, and 3) devising novel solutions that do not require proprietary knowledge of DRAM chip internals. We believe our experimental results and architecture-level solutions will enable and inspire future works targeting better reliability, performance, fairness, and energy efficiency in DRAM-based systems while DRAM-based memory systems continue to scale to higher density and become more vulnerable to read disturbance. We hope and expect that future works will explore avenues on how to leverage the insights and solutions we provide in this dissertation to enable such advancements in DRAM-based systems.