Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits
Open access
Date
2024-04Type
- Conference Paper
ETH Bibliography
yes
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Abstract
Dynamically scheduled HLS, through dataflow circuit generation, has proven successful at exploiting operation-level parallelism in several important situations where statically scheduled HLS fails. Yet, although existing dataflow circuits support out-of-order execution of different operations, they strictly confine successive instances of the same operation to execute sequentially in program order, which drastically affects the circuit's performance in the presence of a long-latency operation. This is in stark contrast with the reordering freedom customary in superscalar processors that naturally exploit qualitatively more parallelism in a broad class of applications. The goal of this work is to produce dataflow circuits that have reordering capabilities closer to those of out-of-order superscalar processors. This can bring dramatic improvements in some practically important cases, including when outer iterations in nested loops are independent and the inner loop execution has an unavoidable large initiation interval. In various cases, our technique increases throughput by a factor dependent on the initiation interval of the kernel, at a comparatively modest area cost. Show more
Permanent link
https://doi.org/10.3929/ethz-b-000670485Publication status
publishedExternal links
Book title
FPGA '24: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate ArraysPages / Article No.
Publisher
Association for Computing MachineryEvent
Subject
high-level synthesis; dataflow; out-of-order executionOrganisational unit
09761 - Josipović, Lana / Josipović, Lana
Notes
Conference lecture held on March 4, 2024.More
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ETH Bibliography
yes
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