Thermal Analysis and Model Identification Techniques for Logic + WIDEIO Stacked DRAM Test Chip
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Date
2014Type
- Conference Paper
ETH Bibliography
yes
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Abstract
High temperature is one of the limiting factors and major concerns in 3D-chip integration. In this paper we use a 3D test chip (WIDEIO DRAM on top of a logic die) equipped with temperature sensors and heaters to explore thermal effects. We correlated real temperature measurements with the power dissipated by the heaters using model learning techniques. The resulting compact thermal model is able to predict temperatures at chip locations far from the temperature sensors and to infer the power dissipation at any location of the chip. Results are verified by mean of an off-sample validation technique and show a high accuracy of the compact thermal model when compared with silicon measurements. Show more
Publication status
publishedExternal links
Book title
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)Pages / Article No.
Publisher
IEEEEvent
Organisational unit
03996 - Benini, Luca / Benini, Luca
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ETH Bibliography
yes
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