SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems
Abstract
Simple graph algorithms such as PageRank have been the target of numerous hardware accelerators. Yet, there also exist much more complex graph mining algorithms for problems such as clustering or maximal clique listing. These algorithms are memory-bound and thus could be accelerated by hardware techniques such as Processing-in-Memory (PIM). However, they also come with nonstraightforward parallelism and complicated memory access patterns. In this work, we address this problem with a simple yet surprisingly powerful observation: operations on sets of vertices, such as intersection or union, form a large part of many complex graph mining algorithms, and can offer rich and simple parallelism at multiple levels. This observation drives our cross-layer design, in which we (1) expose set operations using a novel programming paradigm, (2) express and execute these operations efficiently with carefully designed set-centric ISA extensions called SISA, and (3) use PIM to accelerate SISA instructions. The key design idea is to alleviate the bandwidth needs of SISA instructions by mapping set operations to two types of PIM: in-DRAM bulk bitwise computing for bitvectors representing high-degree vertices, and near-memory logic layers for integer arrays representing low-degree vertices. Set-centric SISA-enhanced algorithms are efficient and outperform hand-tuned baselines, offering more than 10× speedup over the established Bron-Kerbosch algorithm for listing maximal cliques. We deliver more than 10 SISA set-centric algorithm formulations, illustrating SISA's wide applicability. Show more
Publication status
publishedExternal links
Book title
MICRO '21: MICRO-54: 54th Annual IEEE/ACM International Symposium on MicroarchitecturePages / Article No.
Publisher
Association for Computing MachineryEvent
Subject
Graph Mining; Graph Pattern Matching; Graph Learning; Clique Mining; Clique Listing; Clique Enumeration; Subgraph Isomorphism; Parallel Graph Algorithms; Processing In Memory, Processing Near Memory; Graph Accelerators; Instruction Set ArchitectureOrganisational unit
09483 - Mutlu, Onur / Mutlu, Onur
03950 - Hoefler, Torsten / Hoefler, Torsten
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