A 200MS/s 14b 97mW DAC in 0.18 mu m CMOS

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Author
Huang, Qiuting
Francese, Pier A.
Martelli, Chiara
Nielsen, Jannik
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Date
2004-02
Type
    Conference Paper
Abstract
A fully analog loop calibrates 32 MSB floating current sources in the background to achieve 14b accuracy. Operating at 200MS/s, the 97mW DAC achieves maximum SFDR of 85dB in NRZ mode, 76dB in RZ mode, and maintains -160dBm/Hz noise spectral density. Implemented in 0.18/spl mu/m CMOS, the core area Show more
Publication status
published
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Editor
Fujino, Laura C.
Book title
2004 IEEE International Solid-State Circuits Conference
Journal / series
Digest of Technical Papers / IEEE International Solid State Circuits Conference
Volume
47
Pages / Article No.
364 - 365
Publisher
IEEE
Event
2004 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, February 15-19, 2004
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yes
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