A 0.026mm2 5.3mW 32-to-2000MHz Digital Fractional-N Phase Locked-Loop Using a Phase-Interpolating Phase-to-Digital Converter
dc.contributor.author
Jang, Taekwang
dc.contributor.author
Nan, Xing
dc.contributor.author
Liu, Frank
dc.contributor.author
Shin, Jungeun
dc.contributor.author
Ryu, Hyungreal
dc.contributor.author
Kim, Jihyun
dc.contributor.author
Kim, Taeik
dc.contributor.author
Park, Jaejin
dc.contributor.author
Park, Hojin
dc.date.accessioned
2019-03-21T09:35:27Z
dc.date.available
2019-03-20T11:16:15Z
dc.date.available
2019-03-20T14:28:40Z
dc.date.available
2019-03-21T09:35:27Z
dc.date.issued
2013
dc.identifier.isbn
978-1-4673-4516-3
en_US
dc.identifier.isbn
978-1-4673-4515-6
en_US
dc.identifier.other
10.1109/ISSCC.2013.6487723
en_US
dc.identifier.uri
http://hdl.handle.net/20.500.11850/332567
dc.language.iso
en
en_US
dc.publisher
IEEE
en_US
dc.title
A 0.026mm2 5.3mW 32-to-2000MHz Digital Fractional-N Phase Locked-Loop Using a Phase-Interpolating Phase-to-Digital Converter
en_US
dc.type
Conference Paper
dc.date.published
2013-03-28
ethz.book.title
2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
en_US
ethz.pages.start
254
en_US
ethz.pages.end
255
en_US
ethz.event
IEEE International. Solid-State Circuits Conference. Digest of Technical Papers (ISSCC 2013)
en_US
ethz.event.location
San Francisco, CA, USA
en_US
ethz.event.date
February 17-21, 2013
en_US
ethz.publication.place
Piscataway, NJ
en_US
ethz.publication.status
published
en_US
ethz.leitzahl
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::09647 - Jang, Taekwang / Jang, Taekwang
en_US
ethz.leitzahl.certified
ETH Zürich::00002 - ETH Zürich::00012 - Lehre und Forschung::00007 - Departemente::02140 - Dep. Inf.technologie und Elektrotechnik / Dep. of Inform.Technol. Electrical Eng.::02636 - Institut für Integrierte Systeme / Integrated Systems Laboratory::09647 - Jang, Taekwang / Jang, Taekwang
ethz.date.deposited
2019-03-20T11:16:17Z
ethz.source
BATCH
ethz.eth
no
en_US
ethz.availability
Metadata only
en_US
ethz.rosetta.installDate
2019-03-20T14:28:47Z
ethz.rosetta.lastUpdated
2019-03-21T09:35:33Z
ethz.rosetta.exportRequired
false
ethz.rosetta.versionExported
true
ethz.COinS
ctx_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.atitle=A%200.026mm2%205.3mW%2032-to-2000MHz%20Digital%20Fractional-N%20Phase%20Locked-Loop%20Using%20a%20Phase-Interpolating%20Phase-to-Digital%20Converter&rft.date=2013&rft.spage=254&rft.epage=255&rft.au=Jang,%20Taekwang&Nan,%20Xing&Liu,%20Frank&Shin,%20Jungeun&Ryu,%20Hyungreal&rft.isbn=978-1-4673-4516-3&978-1-4673-4515-6&rft.genre=proceeding&rft_id=info:doi/10.1109/ISSCC.2013.6487723&rft.btitle=2013%20IEEE%20International%20Solid-State%20Circuits%20Conference%20Digest%20of%20Technical%20Papers
Dateien zu diesem Eintrag
| Dateien | Größe | Format | Im Viewer öffnen |
|---|---|---|---|
|
Zu diesem Eintrag gibt es keine Dateien. |
|||
Publikationstyp
-
Conference Paper [35595]