HERO: an Open-Source Research Platform for HW/SW Exploration of Heterogeneous Manycore Systems
Abstract
Heterogeneous systems on chip (HeSoCs) co-integrate a high-performance multicore host processor with programmable manycore accelerators (PMCAs) to combine “standard platform” software support (e.g. the Linux OS) with energy-efficient, domain-specific, highly parallel processing capabilities.
In this work, we present HERO, a HeSoC platform that tackles this challenge in a novel way HERO’s host processor is an industry-standard ARM Cortex-A multicore complex, while its PMCA is a scalable, silicon-proven, open-source many-core processing engine, based on the extensible, open RISC-V ISA.
We evaluate a prototype implementation of HERO, where the PMCA implemented on an FPGA fabric is coupled with a hard ARM Cortex-A host processor, and show that the run time overhead compared to manually written PMCA code operating on private physical memory is lower than 10 % for pivotal benchmarks and operating conditions. Thus, HERO demonstrates that ARM and RISC-V can productively coexist in a dual-ISA HW-SW platform. Mehr anzeigen
Persistenter Link
https://doi.org/10.3929/ethz-b-000314220Publikationsstatus
publishedExterne Links
Verlag
Association for Computing MachineryKonferenz
Thema
Parallel Architectures; Heterogeneous (hybrid) systems; System on a chip; Reconfigurable Logic and FPGAs; Parallel programming languageOrganisationseinheit
03996 - Benini, Luca / Benini, Luca