A Jitter Programmable Digital Bang-Bang PLL Using PVT-Invariant Stochastic Jitter Monitor

Abstract

We propose a digital bang-bang phase locked-loop (DBPLL) whose output rms jitter can be set to a user-defined value. By using a stochastic jitter monitoring circuit (JMC) and automatic loop bandwidth control, the proposed BBPLL can adjust its power consumption to obtain the desired target jitter during its initial set-up, regardless of conditions in process, voltage, and temperature (PVT). Implemented in 28 nm CMOS, the prototype PLL achieves rms jitter within 0.26 ps difference of the target jitter under various PVT conditions while operating at 2.88 GHz and achieving FoM of -225 dB which is state-of-the-art for ring oscillator-based BBPLLs.