A 200MS/s 14b 97mW DAC in 0.18 mu m CMOS

Abstract

A fully analog loop calibrates 32 MSB floating current sources in the background to achieve 14b accuracy. Operating at 200MS/s, the 97mW DAC achieves maximum SFDR of 85dB in NRZ mode, 76dB in RZ mode, and maintains -160dBm/Hz noise spectral density. Implemented in 0.18/spl mu/m CMOS, the core area is less than 1mm/sup 2/.