Metadata only
Datum
2005-08Typ
- Conference Paper
ETH Bibliographie
yes
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Abstract
A 4GHz integer-N frequency synthesizer is realized in a 0.13μm CMOS technology. It has a 400kHz reference frequency and 40kHz loop bandwidth such that 2GHz quadrature LO signals can be generated after a divide-by-two, with channel raster of 200kHz. The measured in-band phase noise is -74dBc/Hz @4kHz offset. A self-regulated charge pump is proposed to improve matching as well as charge sharing. Reference spurs are thereby kept below -55dBc over the VCO tuning voltage from rail to rail. The requirements for UMTS transceiver have been fulfilled with an overall power consumption of 9.5mW, which is the lowest reported to date. Core area of the chip is as small as 0.2mm2 Mehr anzeigen
Publikationsstatus
publishedExterne Links
Buchtitel
ISLPED’05: Proceedings of the 2005 International Symposium on Low Power Electronics and DesignSeiten / Artikelnummer
Verlag
Association for Computing MachineryKonferenz
Thema
WCDMA; Frequency synthesizer; Phase-locked loop; Low power; CMOSOrganisationseinheit
03380 - Huang, Qiuting (emeritus) / Huang, Qiuting (emeritus)
ETH Bibliographie
yes
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