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A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS
(2007)Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2007 IEEE International Solid-State Circuits Conference (ISSCC)A quarter-rate CDR circuit is based on a dual-loop approach where sampling phases are generated by a phase-programmable PLL that is controlled by a digital DLL. Implemented in 65nm SOI CMOS, the chip occupies 0.03mm 2 and consumes 1.8mW/Gb/s. Measurements confirm 40Gb/s operation with a BER <10 -12 at a maximum frequency-offset of 400ppm. The phase relation between data and edge samples can be programmed within plusmn0.1 UI.Other Conference Item -
A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI
(2007)Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2007 IEEE International Solid-State Circuits Conference (ISSCC)A half-rate source-series terminated TX, operating at data-rates up to 16Gb/s, targets chip-to-chip on-board interconnects. The TX features a 4-tap FFE, tunable termination, and clock-cleanup circuitry for low duty-cycle distortion, and is capable of driving loads referenced to a variable termination voltage, including Gnd, V DD , and V DD /2. Implemented in 65nm SOI, it occupies an area of 230 times 56mum 2 and draws 57.5mA from a 1V ...Other Conference Item -
A Linear Uplink WCDMA Modulator with 156dBc/Hz Downlink SNR
(2007)Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2007 IEEE International Solid-State Circuits Conference (ISSCC)A linearity-boosting technique for upconversion mixers enables a 0.13 μm CMOS WCDMA modulator to achieve -49dBc ACLR and -l56dBc/Hz SNR. The chip consumes 113mW from a 1.2V supply. It is suitable for SAW-filter-free TX implementations. Results show that this technique improves the mixer IIP3 by 6dB.Other Conference Item -
EVE: A framework for running virtual reality experiments in neuroscience
(2018)Experiments in neuroscience often rely on virtual reality (VR) to investigate navigation inside the MRI scanner. While these studies are limited by the lack of locomotion and proprioceptive feedback, researchers have successfully immersed participants using passive (e.g., videos, images) or active (e.g., movement mediated by a control interface) virtual environments in order to study different aspects of their spatial memory. However, ...Other Conference Item -
A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode ΔΣ ADC with -92dB THD
(2007)Digest of Technical Papers / IEEE International Solid State Circuits Conference ~ 2007 IEEE International Solid-State Circuits Conference (ISSCC)A 2-2 cascaded multi-standard DeltaSigma modulator achieves a OR of 88/79/67dB in EDGE/UMTS/WLAN mode, respectively. With a high linearity of -92dB THD and 34dBm IIP3 for EDGE, this ADC is suitable for wireless applications. Implemented in 0.13 μm CMOS and occupying 0.4mm 2 , the modulator covers 0.1-to-10MHz signal bandwidth with scalable power consumption between 2.9 and 20.5mW from a 1.2V supply.Other Conference Item -
A microfluidic platform for the investigation of the cononsolvency effect in pNIPAM microgels
(2019)Thermodynamik-Kolloquium 2019. Book of AbstractsOther Conference Item -
On the origin of the default categorical structure in spatial memory
(2015)Abstract Book of Psychonomic Society's 56th Annual MeetingOther Conference Item -
Evaluation of Robustness of Kinetic Analysis to Noise for Hyperpolarized [1-13C] Pyruvate Metabolism in the Heart
(2012)Other Conference Item -
Synchrotron-Based High Resolution THz Spectroscopy Between 0.8 and 3 THz Using a Collisional Cooling Multireflection Cell
(2015)The 24th Colloquium on High Resolution Molecular Spectroscopy: Book of AbstractOther Conference Item -
Dynamic 3D T1 TFE Images of the Orbit with High Spatiotemporal Resolution at 3T
(2012)20th Annual ISMRM scientific meeting and exhibition 2012 : Melbourne, Australia, 5 - 11 May 2012Other Conference Item